发明名称 MULTI-CPU SYSTEM
摘要 <p>PURPOSE:To prevent the wrong actions which are caused with output of the wrong data by providing a function which produces a signal that neglects an interruption and a function which masks the interruption applied to each central processing signal during the output of the signal neglecting the interruption and starting simultaneously the control of all CPUs. CONSTITUTION:The signals X1 - Xn showing the initialization states are produced by the CPU 1 - CPU n, and the data on these signals are latched as the data XX1 - XXn. Then the interruption of the TXX is neglected if even one of data XX1 - XXn is kept in an initialization state. Then the interruption of the TXX is accepted only when all CPUs are through with their initialization, and the cycle heads of interruptions applied to the CPU 1 - CPU n are made even. Then all CPUs are started at one time after these CPUs are prepared. Thus the control cycles of all CPUs are made even. Then it is possible to evade such a case where a wrong action is caused with output of a wrong signal.</p>
申请公布号 JPH04131961(A) 申请公布日期 1992.05.06
申请号 JP19900251837 申请日期 1990.09.25
申请人 TOSHIBA CORP 发明人 AKIYAMA SACHIKO
分类号 G06F15/177;G06F1/24;G06F15/16 主分类号 G06F15/177
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