| 摘要 |
PURPOSE:To attain high accuracy and to reduce power consumption by obtaining a path for a logic gate in a way that a delay time of a delay circuit is closer to an object delay time to the utmost and setting a selector in matching with the obtained path. CONSTITUTION:In the delay adjustment mode (a line 1201 set to an L level), a delay control circuit 1200 calculates a period from an output 1303 of a frequency counter 1300, and the period is helved to be an actual delay if a digital delay circuit 1000. The calculated delay and an output 1401 (objected delay) of a resistor 1400 are compared, the quantity of the actual delay is judged with respect to the object delay and a control input 1103 to a delay block 1100 is revised depending on the judged result. Then a frequency is measured with respect to the setting of the control input 1103 after the revision to obtain an actual delay, it is compared with the object delay 1401 and the control input 1103 is reversed depending on the result. The processing above is repeated to control the actual delay in the digital delay circuit 1000 so as to be closer to the object delay to the utmost. Then the mode is changed to the actual operating mode and the digital delay circuit 100 is operated as the substantial delay circuit. |
