| 摘要 |
A sequence matrix for decoding n binary events each having m different states without the need for a clock or a data message preamble. Sequential binary input signals are applied to an input decoder which provides steering signals to a sequence register for storing the sequential information to provide a parallel pure binary word readout. The steering signals are shifted from one storage element in the shift register to another by shift pulses generated from the sequential input signals. A timing circuit triggered by the shift pulses initiates a time gate during which the sequential input signals must be processed or the register will be reset without providing a readout. The decoder readout from the sequence register is displayed on a decoder display.
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