| 摘要 |
PURPOSE:To make repair easy by drawing up only a part of wiring pattern being an object of repair to the upper layer without forcibly drawing up a wiring being not an object of the repair. CONSTITUTION:A signal wiring for connecting the cell terminal 5 of a logic gate 1 and the cell terminal 6 of a logic gate 2 is a wiring being an object of repair and that connecting the cell terminal 7 of a logic gate 3 and the cell terminal 8 of a logic gate 4 is a wiring being not an object of repair. In this case, when a multilayer interconnection is conducted, a wiring 25 for drawing up the cell terminal 5 to the highest layer is conducted relative to the cell terminals 5 and 6 and the fifth layer is provided with a corresponding cell terminal 21. Then, a wiring 26 for drawing up the cell terminal 6 to the highest layer is conducted and the fifth layer is provided with a corresponding cell terminal 22. The cell terminals 7 and 8 are placed in the lower first layer as they are and the wiring between the cell terminals 7, 8 is subjected to a wiring process by the automatic wiring of wiring algorithm. Then, a signal wiring is conducted for connecting the cell terminals 5 and 6. Thus, a semiconductor integrated circuit chip repair for changing a wiring can be conducted easily. |
