发明名称 PHASE CONTROLLER BETWEEN INPUT/OUTPUT DATA FOR TRANSMITTER FOR RELAY EXCHANGE
摘要 <p>PURPOSE:To prevent missing of a data by outputting a pseudo signal representing a head of a frame for a period corresponding to a head of the frame with a self-running line frame counter when out of synchronism takes place. CONSTITUTION:A write frame counter 2 is so configurated that it is a self- running counter outputting a pseudo signal representing a head of a frame for a period corresponding to the frame head when the counter 2 does not receive a signal representing the head of the frame by a synchronization detection section 5. Thus, the counter 2 consists of an adder 2A, a reset logic section 2A, and an AND circuit section 2C or the like. Thus, when out of synchronism takes place, a level of a synchronizing detection signal *SYNCHEHD remains H and a synchronizing detection signal of an L level is not inputted to the counter 2, the logic 2B outputs an L signal for each of 8 frames and the circuit section 2C outputs '0' by the L signal to keep a phase before out of synchronism and to continue write to a frame aligner 1. Thus, a defect of a data generated at out of synchronism is prevented.</p>
申请公布号 JPH0494251(A) 申请公布日期 1992.03.26
申请号 JP19900210935 申请日期 1990.08.09
申请人 FUJITSU LTD 发明人 FUKUYAMA AKIFUMI
分类号 H04L7/00;H04M7/00 主分类号 H04L7/00
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