发明名称 System for reproducing timing clock signal.
摘要 <p>A timing clock reproducing system in a digital subscriber line communication for extracting an optimum phase of a clock signal, and comprising: a line equalizer (111) for shaping a waveform distorted by a transmission through a cable line; a PLL circuit (112) for generating a sampling timing control signal; an analog-to-digital converter (113) for sampling a signal received from the line equalizer at a timing controlled by the sampling timing control, and for converting the received signal into a digital signal; a decision feedback equalizer (114), for outputting tap coefficients including a precursor equalizing tap coefficient; and an evaluating function deriving means (115) for deriving an evaluating function the based the PLL circuit (112) being controlled by the valuating function for adjusting a sampling timing of the analog-to-digital converter. &lt;IMAGE&gt;</p>
申请公布号 EP0476487(A2) 申请公布日期 1992.03.25
申请号 EP19910115278 申请日期 1991.09.10
申请人 FUJITSU LIMITED 发明人 MIYOSHI, SEIJI, FUJITSU IBUKINO SHATAKU A202;SATO, TAKASHI;TAKATO, KENJI, PAKUHAITSU YURIGAOKA 106;UJIIE, HIROYUKI;IKETANI, YOZO, DAI-3 EBISUSO 102;KAWADA, KINJI;FUKUDA, MISAO;ITOKAWA, HIROAKI;UENO, NORIO;AWATA, YUTAKA;TOKIWA, KOUJI
分类号 H04L7/02 主分类号 H04L7/02
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