发明名称 TIMING SIGNAL GENERATING CIRCUIT
摘要 PURPOSE:To prevent the fluctuation of the block level of an output signal by generating both a vertical transfer clock and a horizontal transfer clock with the read output of an ROM, and stopping the operation of an inside counter in a prescribed time since the start of a horizontal blanking period. CONSTITUTION:A pulse SH3 is supplied to a horizontal clock circuit 4 by supplying both a clock CLKN and a reset pulse PRH generated in a synchronous circuit 1a to the first counter 1b and addressing a horizontal ROM 2. Then, horizontal transfer clocks SH1 and SH2 are generated from a horizontal clock circuit 4. Also, vertical transfer clocks V11-V44 are generated from a vertical clock circuit 5. Then, the operation of an inside counter 1 is stopped in the prescribed time since the start of the horizontal blanking period. Thus, the fluctuation of the black level can be removed without generating the difference of level of the black level in an OPB (optical black) level pickup area due to the power voltage fluctuation or the like.
申请公布号 JPH0492582(A) 申请公布日期 1992.03.25
申请号 JP19900207982 申请日期 1990.08.08
申请人 SONY CORP 发明人 MIYATA KATSURO
分类号 H04N5/067;H04N3/14;H04N5/16;H04N5/335;H04N5/357;H04N5/369;H04N5/372;H04N5/378 主分类号 H04N5/067
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