| 摘要 |
PURPOSE:To decrease processing steps by cascading plural unit circuits of one-sample delay units and adders to the output side of a multiplier. CONSTITUTION:The unit circuits 60, 70, and 80 equipped with one-sample delay units 60-1 - 60-n, 70-1 - 70-n, and 80-1 - 80-n cascaded in plural stages so as to delay input signals, sample by sample, and adders 61-1 - 61-n, 71-1 - 71-n, and 81-1 - 81-n which are cascaded in plural stages so as to add the outputs of the respective one-sample delay units are cascaded to the output side of the multiplier 50. Then the one-sample delay units 60-1 - 60-n on the unit circuit 60 in the initial stage delay the output of the multiplier 50, sample by sample, and the adders 61-1 and 61-n of the unit circuit 60 adds the outputs of the respective one-sample delay units 60-1 - 60-n in order. Further, the unit circuits 70 and 80 in the following stages adds the outputs of the unit circuits 60 in precedent states similarly while delaying them, sample by sample. Consequently, the calculation of a covariance matrix is simplified. |
