| 摘要 |
An integrated circuit device having a memory array of memory cells in which the total number N of unique available memory addresses is a power of two, yet wherein neither the number of columns nor the number of rows of cells is a power of two. This permits the chip die size and height/width ratio to be optimized. The device further includes a circuitry for generating address selection signals, providing a total number of unique addresses equal to N, leaving unused some of the memory cells comprising the array.
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