| 摘要 |
"Phase-Locked Clock Regeneration Circuit for Digital Transmission Systems" In a digital transmission system, a clock regeneration circuit includes a phase-locked loop having a low-pass filter, a voltage-controlled oscillator connected thereto, and a phase comparator for supplying to the low-pass filter a signal representative of the phase difference between an incoming two-level data bit stream and the output of the voltage-controlled oscillator. The incoming data bit stream is converted into a plurality of parallel data bit streams and fed to a multi-level quadrature amplitude modulator in response to a clock signal derived from the output of the voltage-controlled oscillator and converted into an outgoing multi-level digital signal. An incoming CMI (coded mark inversion) coded binary signal is sampled by a flip-flop for in response to the output of the voltage-controlled oscillator to supply an output signal to the VCO through the low-pass filter. |
