| 摘要 |
<p>Memory apparatus serving a data supplying device, the memory apparatus including a plurality of at least n+1 memory elements (610-630), each memory element including a multiplicity of memory cells, wherein at least one memory cell in at least one of the n+1 memory elements (610-630) is defective, and a defective memory element controlling device (640) operative to control the plurality of memory elements including a least one defective memory element so as to obtain timing at least as rapid as the timing of a plurality of n perfect memory elements without providing additional physical connections to the data supplying device.</p> |
