| 摘要 |
PURPOSE:To simplify the test of a circuit to be tested and to decrease the test time by adding an initial value setting circuit to the frequency dividing circuit so that the phase of a basic clock and a 1/2 frequency division clock is always fixed at the time of starting the test. CONSTITUTION:When a clock timing is inputted from a clock input terminal CLKIN, a basic clock CLK2f is outputted through inverters 1, 2. Simultaneously, a 1/2 frequency division clock CLKf is outputted from a frequency dividing circuit comprising latch circuits 3, 4 applying 1/2 frequency division to the clock inputted from the input terminal CLKIN. An initial value setting circuit 5 sets the output QC of the master side latch circuit 3 to an H level to fix the phase of a basic clock CLK2f and the 1/2 frequency division clock CLKf at the time of starting clock application. |
