发明名称 PACKAGE FOR SEMICONDUCTOR DEVICE
摘要 PURPOSE:To prevent the generation of a warpage of a package, by providing through holes for reducing the warpage, which are bored at one or more places in a metallic frame. CONSTITUTION:A mount metallization pattern 101-1 for fastening and gronding a semiconductor device, a seal metallization pattern 101-2 for sealing a cap, and draw-out metallization patterns 101-4 for drawing out the electrodes of the semiconductor device to the outside, etc., are provided on an insulation base board 101 made of ceramics, such as alumina, beryllia or AlN. Leads 105 for drawing out the electrodes of the semiconductor device to the outside and a metallic frame 102 for grounding the semiconductor device are brazed to the insulation base board 101 via a brazing material 106 such as Ag-Cu alloy or Au-Ge alloy. Longish through holes 107 for reducing warpages are bored in the metallic frame 102. Thereby, the warpage and stress of a package, which are generated due to the difference between the coefficients of thermal expansion in the case of assembling the insulation base board and the metallic frame by brazing, can be reduced.
申请公布号 JPH0426144(A) 申请公布日期 1992.01.29
申请号 JP19900131822 申请日期 1990.05.22
申请人 NEC CORP 发明人 HASHIZUME SHOJI;NASU MASAYOSHI
分类号 H01L23/02;H01L23/498;H01L23/50;H05K1/02;H05K1/05;H05K3/00;H05K3/34 主分类号 H01L23/02
代理机构 代理人
主权项
地址
您可能感兴趣的专利