| 摘要 |
PURPOSE:To easily shorten the frequency pull-in time by taking a phase comparison frequency in the beginning of a pull-in operation high, thereafter, setting the comparison frequency to a target frequency, at the time of turning on a power source in the beginning and at the time of changing an inter-channel frequency. CONSTITUTION:In order to obtain the PLL locking state of a high speed at the time of turning on a power source and at the time of switching a channel, channel data is inputted to a frequency division/comparison shifting register 16 by a data signal 17 and a clock signal 18 from the outside. The inputted data is latched to a data latch 20 or 21 by a latch enable signal 19. The latched data is read in frequency dividers 2, 5, and an oscillation frequency generated by a reference oscillator 1 and a VCO 4 is divided into a phase comparison frequency. In the beginning of latching the data, it is returned to the data of a frequency division ratio in which the frequency is divided into 8-32 folds of a target phase frequency by switches 22, 23, subjected to loop lock once, thereafter, becomes a necessary phase comparison frequency. In this case, the constant of a loop filter 7 is also controlled by a controller 11, and it is pulled in stably to the target frequency. |
