| 摘要 |
PURPOSE:To set arbitrary number of stages by controlling the number of the areas of RAMs used as shift registers by changing the maximum count values of first and second counters which designate read and write addresses on the RAM. CONSTITUTION:An input side system converts input data to a parallel data string with a serial-parallel converter 1 when a clock is inputted, and writes the data on the address of the RAM 6 designated sequentially by a counter 9 via a buffer 5 synchronizing with the clock. Meanwhile, an output side system reads out the data from the address of the RAM 6 designated by a counter 10 synchronizing with the clock when the clock is inputted, and outputs the data read out from the RAM 6 by converting from the parallel data to serial data with a parallel-serial converter 8. No problem such as the omission of data, etc., occurs even when no synchronism of the clock is taken until the maximum value or the minimum value represented by both counters is obtained. |
