| 发明名称 |
Method and apparatus for latency reduction |
| 摘要 |
Aspects of the disclosure provide an integrated circuit that includes a plurality of input/output (IO) circuits, an instruction receiving circuit and control circuits. The IO circuits are configured to receive a plurality of bit streams corresponding to an instruction to the integrated circuit. The instruction receiving circuit is configured to form the instruction from the plurality of bit streams. The control circuits are configured to operate according to the instruction. |
| 申请公布号 |
US9377957(B2) |
申请公布日期 |
2016.06.28 |
| 申请号 |
US201414174449 |
申请日期 |
2014.02.06 |
| 申请人 |
Marvell World Trade Ltd. |
发明人 |
Chen Shawn;Jiang Wei;Chen Lin |
| 分类号 |
G06F13/12;G06F13/38;G06F13/00;G06F15/173;G06F3/06;G06F13/42;G06F13/16 |
主分类号 |
G06F13/12 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. An integrated circuit, comprising:
a plurality of input/output (IO) circuits to receive a plurality of bit streams corresponding to an instruction to the integrated circuit; an instruction receiving circuit to form the instruction from the plurality of bit streams; a register to store a value indicative of a configuration based on the instruction; and control circuits to operate according to the value indicative of the configuration so that a first number of IO circuits is used when the value is a first value and a second number of IO circuits is used when the value is a different second value. |
| 地址 |
St. Michael BB |
