Structure and fabrication method for a double trench memory cell device.

摘要

A method is described for fabricating a novel double trench memory structure including a shallow trench (15) access transistor adjacent to a deep trench (11) storage capacitor. The described three-dimensional DRAM cell structure consists of shallow trench access transistors and deep trench storage capacitors in a n-well (12) disposed on a semiconductor substrate (10). In the fabrication method, the vertical access transistors are built adjacent to the one side of one deep substrate-plate trench storage capacitor. The vertical access transistor partially overlaps the storage capacitor. An asymmetric insulation scheme (34) decreases the overlap capacitance between word line (20) and storage node (30). The contact between drain region (26) and storage node (30) is made by selectively powing an epitaxial layer after forming the shallow trench (15). Arrangement of the access transistors and trench storage capacitor are different from that of standard single trench cells. The structure may be fabricated for p-channel or n-channel embodiments. <IMAGE>