发明名称 RESET CIRCUIT
摘要 <p>PURPOSE:To discriminate a reset factor by providing a storage circuit, an interface circuit through which the output of the storage circuit is read out by an external device, and a logic circuit which writes the operation in the storage circuit at the time of power-on reset, manual reset, or auxiliary reset. CONSTITUTION:An inverter 14-1 inverts an output signal 7 of an inverter 4, and the signal on a signal line 9 and an auxiliary reset signal 10 are inputted to a NOR gate 15, and the output of the inverter 14-1 and that of the NOR gate 15 are inputted to a flip flop 13 as the preset input and the clear input respectively. At the time of power-on reset, a signal line 7 goes to the high level for a while, and a PR input of the flip flop 13 goes to the low level by the inverter 14-1, and a Q output 16 goes to the high level. At the time of manual reset auxiliary reset, a CL input goes to the low level by the NOR gate 15, and the Q output 16 goes to the low level. Thus, the reset factor is discriminated.</p>
申请公布号 JPH03282808(A) 申请公布日期 1991.12.13
申请号 JP19900084031 申请日期 1990.03.30
申请人 NEC CORP 发明人 KOIKE TSUNEO
分类号 G06F1/24 主分类号 G06F1/24
代理机构 代理人
主权项
地址