Phase-lock loop device operable at a high speed.

摘要

In a phase-lock loop device for phase locking a device input signal (11) representing a first complex number and having a device input phase which should be locked into a locked phase, a first complex multiplier (14) calculates a first product of the first complex number and a first conjugate complex number to produce a first complex product signal. The first conjugate complex number is represented by a first conjugate signal which is produced by delaying and processing the device input signal. A second complex multiplier (18) calculates a second product of a phase processed signal and a multiplier input signal to produce a second complex product signal. The phase processed signal is produced by filtering and processing the first complex product signal. The multiplier input signal is produced by delaying and limiting the second complex product signal. A third complex multiplier (22) calculates a third product of the first complex number and a second conjugate complex number to produce a third complex product signal. The second conjugate complex number is represented by a second conjugate signal which is produced by processing the second complex product signal. A fourth complex multiplier (24) calculates a fourth product of the second complex product signal and a filtered signal to produce a fourth complex product signal having the locked phase. The filtered signal is produced by filtering the third complex product signal. <IMAGE>