| 摘要 |
<p>PURPOSE:To eliminate the need for a memory for clock transfer by storing a reception data into a memory storing the result of retrieval of synchronization information and reading the reception data with a delay of an optional time. CONSTITUTION:A synchronization information retrieval circuit 4 receives a clock and a data to detect synchronization information and the bit of the information is compared with a check bit in a dual port RAM 1 through an A port. When the result of comparison tells OK, a succeeding check bit is used and when succeeding synchronization information is detected, it is compared with a check bit replaced and stored and when OK, a succeeding check bit is selected, and when a frame pattern is detected, the synchronization information is sent to a receiver. When not OK, it is discriminated to be a data bit and written in the RAM 1. An address generator 2 uses a write control signal to write a received data to an A port of the RAM 1 synchronously with the reception clock and an address generator 3 receives a read control signal of the equipment side and a clock and outputs the received data from a B port of the RAM 1 synchronously with the clock after an optional time. One memory is enough for the purpose and the cost is reduced.</p> |
