发明名称 CLOCK CONTROL SYSTEM BY SCAN-OUT DATA
摘要 PURPOSE:To improve quality by fixing an address in a scan address register. CONSTITUTION:When checking hardware, a fixed scan address register SADR 1 is selected by an address selector SEL 11 so as to always read out a designation signal as scan-out data. At such a time, when the said data is coincident with trigger data 3, a mode set signal 2 is made effective and a clock signal is stopped so that the hardware can be turned to an arbitrary state. Next, when a single cycle mode is set and the signal 2 is made ineffective, an SADR 10 is selected by the SEL 11 and a clock stop signal is canceled. Thus, since the clock is stopped by the arbitrary signal in the hardware so as to confirm the function of the hardware, to investigate a fault or to investigate causes efficiently at the time of debugging, the quality of a computer main body system can be improved.
申请公布号 JPH03265015(A) 申请公布日期 1991.11.26
申请号 JP19900062662 申请日期 1990.03.15
申请人 FUJITSU LTD 发明人 FUKUCHI HIROYUKI
分类号 G06F11/22;G06F1/04 主分类号 G06F11/22
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