| 摘要 |
PURPOSE:To freely change the setting of a delay time by providing a register obtaining a write clock delayed by a time corresponding to a stage number from a head of each FF and number of master clocks from an output terminal of each FF and a multiplexer to the delay device. CONSTITUTION:A write clock RATE is supplied to a data input terminal D of a D FF of a 1st stage of a shift register 6 and a master clock MCLK is given to a clock input terminal CK of each FF. Thus, retarded delay pulses RATE1, RATE2,...RATEn are outputted at a output terminal of each FF. The delay pulse is given to input terminals D1-Dn of a multiplexer 7. The multiplexer 7 decides which of the delay pulses RATE1, RATE2,...RATEn supplied to the input terminals D1-Dn is selected depending on a data ST set to a delay setting register 8. Thus, the setting change in the delay time is implemented freely. |
