发明名称 FAULT RECOVERING SYSTEM
摘要 PURPOSE:To suppress the influence of a fault to a minimum by bracketing the fault to intermittent and fixed ones, deciding whether or not a degenerative operation can be performed when it is the fixed fault, and operating a system with the one on which degeneracy is applied when the degenerative operation can be performed. CONSTITUTION:The occurrence of the fault is informed to a control processor(CP) 3, and the faulty states of fast arithmetic processors (AP) 5-8, a second system control ler (IU) 2, and a second main memory (AM) 10 are employed as a log of faults. A test program (FT) is executed, and the bracketing of the fault to the intermittent and fixed faults is performed. When the execution of the FT is completed normally, it is assumed as the intermittent fault, and the system operation of an interrupted jobs restarted. When abnormality is found out in the execution result of the FT of the AP, it is assumed as the fixed fault, and the log of fault when the fault occurs is employed, and it is decided whether or not the fault is the one on which the degener ative operation with respect to a vector pipeline, cache memory, and the AM can be applied. Constitutional connection information is updated based on a decision result, and the FT is executed in a state where the degeneracy is applied when the fault is the one on which the degenerative operation can be performed, and the operation of the interrupted job is restarted when no fault exists.
申请公布号 JPH03259349(A) 申请公布日期 1991.11.19
申请号 JP19900058619 申请日期 1990.03.08
申请人 NEC CORP;KOUFU NIHON DENKI KK 发明人 JITSUPOU AKIRA;NAKAMURA AKIHIKO
分类号 G06F11/20;G06F11/00;G06F11/14;G06F11/22;G06F15/16;G06F15/177;G06F17/16 主分类号 G06F11/20
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