| 摘要 |
PURPOSE:To reduce the quantity of hardware and to shorten a delay time by dividing multiplication into several steps by a reduced instruction set computer architecture, and executing the multiplication of each step by the same circuit. CONSTITUTION:A multiplication multiplier part instructing means 5 partitions off a multiplier into plural continuous bit parts in order to divide multiplication into plural steps and specifies which bit part out of plural ones is to be multiplied by a multiplicand. The sum of a product of a multiplicand stored in a multiplicand register 1 and one of plural bit parts of a multiplier stored in a multiplier register 2 and a part not defined as a multiplied result out of the contents of a multiplied result storing register 3 is shifted in accordance with a specification outputted from a multiplication multiplier part instructing means 5 and the shifted result is stored in the register 3. The step is repeatedly executed from the lower bit side of the plural bit parts of the multiplication to reduce quantity of hardware and to shorten the delay time. |
