HIGH ORDER SIGMA DELTA OVERSAMPLED ANALOG-TO-DIGITAL CONVERTER INTEGRATED CIRCUIT NETWORK WITH MINIMAL POWER DISSIPATION AND CHIP AREA REQUIREMENTS

摘要

A high order interpolative oversampled (sigma delta) analog-to-digital converter network including a plurality of cascade-coupled integrator stages (22,24,36) is formed on a single integrated circuit chip in a manner that conserves power and chip area. Each integrator stage (22,24,36) includes a differential amplifier, at least one input capacitor and at least one feedback capacitor. The power dissipation and occupied chip area are minimized by down-sizing the chip area occupied by the capacitors and differential amplifiers (op amps) in all but the first integrator stage. The high gain of the first integrator stage makes the noise contribution of subsequent integrator stages negligible so that the higher noise of the subsequent integrator stages is tolerable.