| 摘要 |
A fractional-division synthesizer for a digital transceiver is disclosed in which the fractional divisor may be separated into an integer, N, and a fraction made up of two integers, [n/d]. The integer n is the numerator of the fraction part of the fractional divisor. The integer N is the whole number portion of the fractional divisor. The integer d multiplied by the value of the transceiver channel spacing is algebraically related to the frequency of the reference oscillator. A bit rate clock is also derived from the reference oscillator. |
