DYNAMIC RAM IN WHICH TIMING OF END OF DATA READ OUT IS EARLIER THAN CONVENTIONAL

摘要

A dynamic RAM comprising capacitors (C1, C2) of at least one memory cell each of which stores digital data of one bit as its terminal voltage, bit lines (BLi, B^¨B7L^¨B7i) provided in correspondence with at least one memory cell, gating means (QC1, QC2) provided in correspondence with the capacitors (C1, C2) so as to control electrical connection/disconnection of terminals of the capacitors (C1, C2) to the bit lines (BLi, B^¨B7L^¨B7i), and at least a pair of data bus lines (DB1, DB2) each of which is provided in correspondence with at least one bit line. Currents are fed always from a predetermined power supply (VCC) to the data bus lines (DB1, DB2) via respective predetermined resistors (Q3'', Q4''). Means (Q8'', Q9'') for outputting read out voltages are provided in correspondence with the respective bit lines (BLi, B^¨B7L^¨B7i). The current input terminals of the means (Q8'', Q9'') are connected to the data bus lines (DB1, DB2) corresponding to the bit lines. The means change the voltages of the data bus lines according to the voltage changes generated on the bit lines.