发明名称 POWER-ON RESET CIRCUIT
摘要 <p>PURPOSE:To design a circuit to consume little current and to improve response sped by releasing reset when the power voltage of a microcomputer is high and resetting it when the power voltage is low. CONSTITUTION:In a circuit 1 having the same constitution as the oscillation circuit of the microcomputer, respective transistors are turned on when the power voltage to be impressed is high, and a high level voltage is supplied to a buffer circuit with pull down resistance 2. When the value of the power voltage impressed on the circuit 1 is less than that by which the oscillation circuit does not operate, a current to the degree of a leak current flows in respective transistors of the circuit 1, and the outputs come to almost high impedance, whereby the input-side of the circuit 2 is pulled down. The output of the circuit 2 is connected to the reset terminal of the microcomputer. When the power voltage is high, reset is released and the microcomputer is reset when the power voltage is low and the voltage comes to that with which the oscillation circuit cannot operate. Thus, responsiveness as against the fluctuation of the power voltage improves and the consumption of current is reduced.</p>
申请公布号 JPH03216715(A) 申请公布日期 1991.09.24
申请号 JP19900013048 申请日期 1990.01.22
申请人 NEC CORP 发明人 YOSHIDA OSAMU
分类号 G06F1/24 主分类号 G06F1/24
代理机构 代理人
主权项
地址