| 摘要 |
<p>PURPOSE:To shorten the time required for line switching by providing an address storage section for delay circuit storing a write address of a cell to a common buffer and acting like a delay circuit in addition to an address storage section by an output port. CONSTITUTION:An address storage section 36d for a delay circuit is provided, which stores a write address of a cell to a common buffer 21 and acts like a delay circuit in addition to address storage sections 36a-36c by each output port in a common buffer switch having the address storage sections 36a-36c by each output port storing a write address of a cell to the common buffer 21 by each output port and applying queue processing. After a desired delay is implemented by the address storage section 36d for a delay circuit, an address stored by the address storage section 36d for a delay circuit is read in the older order and the result is fed to the queue of the address storage sections 36a-36c by each output port corresponding to the output port to which the delayed cell is to be outputted. Thus, since no real cell arrival interval detection circuit is required, the time required for line switching is shortened.</p> |
