| 摘要 |
PURPOSE:To carry on the normal working of a system by keeping an invalid state for the detection of errors until the instruction prefetched in a pipeline control system is transmitted out of a pipeline stage when the prefetched instruction is invalidated by a branching instruction. CONSTITUTION:An error detection signal is produced from a data error detecting circuit 5 even when the branching instruction data is set to a register of the final stage. In such conditions, a deciding circuit 9 outputs an output signal to show the production of the error detection signal. Simultaneously, a flag control circuit 11 outputs continuously the validity flags via a flag output circuit 7 until the instruction data set at a register 21 of the first stage is sent out through a register 2m of the final stage in response to the output signal received from the circuit 9. Thus, it is possible to prevent such a mistake where the error caused in the invalidated data is processed by mistake in a pipeline control system which invalidates a prefetched instruction with a branching instruction. |
