| 摘要 |
PURPOSE:To warrant stable operation by adopting a D flip-flop with a reset input terminal, and applying an AND output (wired AND) of each Q output signal of the two D flip-flops to a reset input terminal so as to provide an operation margin to the device in the case of circuit integration. CONSTITUTION:When a phase difference between the Q output signal (CLK1) of a D flip-flop 2 and the Q output signal (CLK2) of a D flip-flop 4 is 60 deg., an active edge of an input clock signal is fed to an input terminal 10 and the high period of Q output of the D flip-flop 2 and the high period of a Q output of the D flip-flop 4 are overlapped for a period from a time t4 to a time t5, then the Q output of the D flip-flop 4 is reset just after a time DELTAT (a delay time till the Q output is changed) after the time T4 actually. Then the Q output of the D flip-flop 3 transits from a low level to a high level at the arrival of the succeeding trailing edge of the input clock signal (t6) and 1/3 frequency division operation at a new phase is started with the D flip-flop 4. |
