| 摘要 |
A direct memory access control system provides for the high speed burst transfer of data blocks from a data source to a data destination. The system includes a first processor for identifying one or more data blocks for transfer from a data source to a data destination and prepares a data structure defining the data transfer required for the transfer of the data block. A second processor, responsive to an enable signal, autonomously generates addressing signals and data transfer signals to effect the transfer of a data block from the data source to the data destination. Upon completion of a transfer, the second processor generates a transfer done signal. A third processor, responsive to the first processor, is provided to initialize the second processor for the transfer of a data block determined by the defining data structure as prepared by the first processor. The third processor, in response to the transfer done signal, initializes the second processor and provides the enable signal autonomously with respect to the first processor. |
