| 摘要 |
PURPOSE:To obtain a Josephson integrated circuit capable of outputting at a slow clock by providing a latching means to clear output data which hold a clear signal being supplied, and a data output means to output a clear instruction corresponding to the output of the output data to supply to the latching means. CONSTITUTION:A latching means 11 to which output data and a conditional signal is supplied from a Josephson processor 10 to hold the output data corresponding to the conditional signal, and clears the output data to hold a clear signal being supplied, and a data output means 12 to which the output data held by the latching means 11 are supplied to output them at second clock speed, and moreover outputs a clear instruction corresponding to the output of the output data and supplies to the latching means 11 are provided. Then, the output data held by the latching means 11 are transferred to the data output means 12 at a second slow clock corresponding with the action speed of a peripheral circuit and are held. Thus, a Josephson integrated circuit which attains reading the output data slowly is obtained.
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