| 摘要 |
<p>A cache tag memory device has a dual port memory array for containing cache tags. One port, accessed by a local processor, can read from and write to the array. The other port is accessed through a global system bus, and can only read the memory array. A storage bit associated with each entry in the array is used as a valid bit. A cache tag entry match can never be made when such valid bit indicates that the entry is invalid. Both ports operate asynchronously from each other. The local port operates much like as SRAM during write and read operations. The global port always monitors the system bus, or snoops, and compares internal RAM data to the external system address. If an entry matches a system address during a system write operation, the corresponding valid bit is set to a value which indicates that the entry is invalid. <IMAGE></p> |
