| 摘要 |
A matrix of multiplexed synchronous binary counters for an integrated circuit comprising a sequence of m counter cells (CC1, CCm) each provided with an individual data input link (Din.1, Din.m) and an individual data output link (Dout.1, Dout.m), and controlled by means of common links comprising a clock link (Clk) for synchronization, a load link (LOAD), and n select links (LS1 to LSn). Each counter cell (CC) includes n memory cells (CM1 CMn), each organized around a unique memory element (B1 to Bn) which is individually selectable by means of the select links (LS1 to LSn), which cells are connected in parallel between the individual data input link (Din) and the individual data output link (Dout) of the said counter cell (CC), and share a common loop memory element (BR) having its data input connected to the individual data ouput link of the counter cell under consideration (CC) via an incrementation circuit.
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