| 摘要 |
PURPOSE:To reduce the capacitance between bit lines and the stray capacitance of bit lines, by arranging the bit lines at the position lower than a capacitor, and forming an insulating layer region wherein the upper electrode of the capacitor does not exist above the upper part of the bit lines. CONSTITUTION:A plurality of word lines WL1-WL7 and a plurality of bit lines B0-B1 perpendicular to the word lines are formed on the main surface of a p-type Si substrate 20. A plurality of memory cells MC are arranged so as to obliquely intersect the lines B0-B1. A capacitor 10 is constituted of a build-up structure of a lower electrode 11, a dielectric layer 12, and an upper electrode 13. In this constitution, the lines B0-B1 are formed at the position lower than the capacitors 10, which are arranged between the adjacent bit lines. Further, also in the peripheral region of a contact part 8 of the lines B0-B1, an aperture part 15 is formed in the electrode 13 of the capacitor 10, and therefore an electrode layer does not exist above the lines B0-B1 in the aperture part. Hence stray capacitance can be reduced. |
