DIGITAL VERTICAL SYNCHRONIZATION SEPARATING CIRCUIT

摘要

The circuit is for digitally separating the vertical sync. signal from the composite sync. signal. The circuit comprises a flip-flop (DF1) receiving the input clock (SS4) signal and the composite sync. signal, an up/down counter (10) for counting the high and low level signals, a random logic (20) for detecting each pulse width, an output control section (30) for producing the latched output, and a clock cutoff section for controlling the up/down counter.