| 摘要 |
<p>PURPOSE:To enlarge a level margin and to transfer data without missing a data load latch by providing a complementary MOS transfer gate between the data load latch and a memory cell array. CONSTITUTION:When a gate TGi is turned to an ON state, for the potentials of a bit line BLi and an input/output node NODEi, the levels are determined according to the program of a memory cell with a ground potential or a power supply voltage Vdd level as an arrival level. Namely, for the CMOS transfer gate TGi, the precharge arrival level to be transmitted to the line BLi is permitted until the voltage Vdd. When the NODEi of a flip-flop FFi is discharged on the side of the line BLi, the discharge arrival level is permitted until the ground potential. Thus, the level margin for the page data load latch to normally latch logic 1 data and logic 0 data is enlarged and the data can be transferred without fail.</p> |
