| 摘要 |
PURPOSE:To apply many address modes without requiring any special read instruction for error correction by providing a parity check and data holding means and a sense voltage switching and address holding means. CONSTITUTION:The parity check and data holding means 10 holds the parity check result of data read out of the EEPROM 2 until a next read is made according to a read instruction that a control circuit such as a general computer 1, etc., has. The sense voltage switching and address holding means consisting of the data holding circuit 10 and an address latch circuit 12 switches the sense voltage of the EEPROM 2 with the output of the data holding means and holds the read address similarly until a next read is made. Consequently, any special read instruction for error correction is required and addressing modes are not limited to one. |
