| 摘要 |
PURPOSE:To simplify schematic and to suppress error missing probability by providing registers more than the width of input test data and feeding back only the output of the final register to the first exclusive OR element. CONSTITUTION:Respective bits of the test data 1(x) inputted to the exclusive OR elements 20 - 2n-1 constituting the respective stages of shift registers are successively operated along with the operation results of the elements of the previous stages and the operation result of the final stage is delayed to be fed back to the element 20 of the first stage from the resistor 3n constituted of the FF further connected in the rear of the final stage. In such a case that the register 3n is added, when all inputs are erroneous, that is, the error probability P in a test pattern is 1, the elements 20 - 2n-1 become zero only when shift is performed by the number K of stages of registers 3. In other words, error missing probability Pal becomes 1/K at the time of P=1. The Pal is converged to 1/2K at the time of 0<P<1. Therefore, only by adding some registers 3, an error detection ratio is obtained without requiring the new elements 2 and schematic is simplified. |
