Multiprocessor system e.g. for digital telephone station - performs readiness check of each sub-processor by master processor before assigning addresses

摘要

The system comprises a master processor (MP) and a number of sub processors (P1...PX) coupled to the latter via a communication line (KL). Each of the sub processors (P1...PX) is brought into a refined outset condition when a reset pulse is supplied, beginning with the first sub processor (P1), each sub processor (P1...PX) subjected to a function check by the master processor (MP), to indicate its readiness condition, before an individual address is assigned. When no further readiness signals are received by the master processor (MP) after a defined time interval a signal is supplied indicating that the processor system is complete. ADVANTAGE - Simple processor system configuration.