Semiconductor memory device.

摘要

A compact, high speed EEPROM is disclosed. The design features mirror-image pairs of cells with a common junction buried under a thick oxide(e.g. 13). The oxide(e.g. 13) also supports a portion of the control(e.g. 25) and floating(e.g. 23) gates. A single erase gate(e.g. 59), also above the oxide(e.g. 13), is capable of erasing two rows of cells at once. Each cell also has a seond junction(e.g. 63) which contacts the semiconductor substrate surface. The second junction(e.g. 63) has a conductive landing pad(e.g. 75) which facilitates small cell size.