发明名称 DELAY CIRCUIT
摘要 <p>PURPOSE:To realize a delay circuit with ease of circuit integration by constituting the circuit with a 1st MOS field effect transistor(TR), a 2nd MOS field effect TR, a resistor, an operational amplifier, a capacitor and a detection circuit. CONSTITUTION:The circuit is constituted of a 1st MOS field effect TR M1, a 2nd MOS field effect TR M2, an operational amplifier A1, a bias means comprising A2, Q1, Q2, R1-R3, a capacitor C and a detection circuit INV. An inverting input terminal of the operational amplifier A1 connects to a source S2 of the 2nd MOS field effect TR M2, an output terminal is introduced to a gate G2 and a DC voltage is fed to a noninverting input terminal from the bias means comprising A2, Q1, Q2, R1-R3. Thus, the effect on temperature fluctuation and delay time fluctuation due to manufacture process fluctuation is relaxed and circuit integration is facilitated.</p>
申请公布号 JPH03109812(A) 申请公布日期 1991.05.09
申请号 JP19890248492 申请日期 1989.09.25
申请人 TDK CORP 发明人 ISHIHARA TSUTOMU;TOMIOKA YASUSHI;YAMANOI YASUTOMO
分类号 H03K5/13 主分类号 H03K5/13
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