| 摘要 |
"Interference Immune Digital Modulation Receiver" A 2n-level demodulated signal- is resolved into 2(n+m) equal intervals by an (n + m)-bit A/D converter (12) and an (n + m)th significant bit is produced from the LSB output of the converter as a representation of an interfering signal contained in the demodulated signal, where m is equal to or greater than unity. A subtractor (5p, 5q; 32p, 32q) cancels the interfering signal with a cancelling signal supplied from a feedback control circuit (9, 11, 7; 16-19; 30-31) which derives it by controlling the amplitude of the (n + m)th significant bit in accordance with the amount of the interfering signal still present in the output of the subtractor. |
