Digital time base generator with adjustable delay between two outputs.

摘要

A digital time base generator circuit is provided having a first phase locked loop (12) for multiplying a reference frequency (f0) by an integer amount and a second phase locked loop (22) for multiplying the reference frequency by a different integer amount. The first and second multiplied reference frequencies are then divided back down to the original reference frequency by two dual modulus frequency dividers (19,29). In this manner a start signal (33) and a stop signal (34) are generated such that the frequency of the start and stop reference signals is the same as the original reference frequency (f0) and the time delay between an edge of the start signal and edge of the stop signal can be changed by altering the mode of either of the dual modulus frequency dividers (19,29).