| 摘要 |
<p>An improved decoder circuit suitable for decoding an encoded binary data stream. The encoding is expected to generate a three-part code format, the format, in turn, comprising a pair of clock transitions that set-off a data transition. The improved decoder circuit establishes whether or not the expected format is in fact realized under arbitrary operating conditions, and in the event of a failure to realize the expected format, provides a suitable format for a subsequent decoding procedure.</p> |
