| 摘要 |
A write-through cache (14) wherein for write operations of less than a word in length the write data stored within a FIFO memory device (18) associated with a first bus agent reflects the result of a read/modify/write type of access wherein a byte or half word has been merged by a local processor (12) with a cache word. Memory control lines driven to a system bus (20) indicate to a memory controller (22) that a write operation is to be accomplished as a word write, thereby eliminating the additional time required to achieve a read/modify/write memory controller cycle. To prevent the occurrence of a problem wherein another bus agent, such as another CPU or an I/O device, writes to a system memory (24) during an interval of time that the word of data is temporarily buffered within the FIFO there is provided circuitry for detecting an external write made to the system memory. Circuitry is also provided for detecting that the FIFO has data stored within and for changing the memory command lines to indicate, instead of a word write, a byte write of a half-word write operation. |
