| 摘要 |
PURPOSE:To increase the accuracy without increasing the number of bits at a D/A converter part, by supplying the output of a counting circuit to a delaying circuit part and extracting the prescribed output of a delaying FF circuit via a gate circuit. CONSTITUTION:The output of a counting circuit is supplied to a delaying circuit part formed by giving a cascade connection among delaying FF circuits 11-14 that work by a clock input. At the same time, the prescribed output of the delaying FF circuit is extracted via gate circuit parts 15-17. In this case, the digital data X1 and X0 are (10) each and the output Q3 is produced only at the output terminal of an AND gate circuit 16 to which no data X0 is supplied. Thus signals Q1 and Q3 are applied to an OR gate 20, and the input D of a delaying FF20 is shown as D= Q1VQ3. Then D/Aout is delivered to a terminal 22. This D/A output is filtered through a low-pass filter to carry out a D/A conversion of 12 bits. |
