Address control for DRAM - has number of continuous connectable to number of memory boards, and timer signal generator for time control

摘要

The timer signal is used for an address signal multiplexing for the DRAM. An input stage applies an address signal of preset bit width. A part of the address signal is selected by an address selection, supplied in response to the timing signal. A branch-off device supplies another part of the address signal from the input stage to respective part of connectors. A second branch-off device supplies the address signal of the multiplexed part from the address selector to the corresp. part of the connector. Pref., the timer signal generator provides two timing controls, generating a combination of sequential line and column addresses. ADVANTAGE - Improved address supply and facility for memory card combination.