发明名称 Method of fabricating interconnections to I/O leads on layered electronic assemblies
摘要 Interconnect circuitry is formed on a selected face of several separate layered electronic assemblies simultaneously. This circuitry interconnects the I/O leads on each assembly, and it is formed by the steps of: (a) placing a plurality of the assemblies in a fixture with spacers between each assembly; (b) aligning to a single plane, one face of each assembly in the fixture on which the circuitry is to be formed; (c) mechanically squeezing the assemblies and spacers together with the fixture such that the aligned faces are held in the single plane and are exposed; (d) depositing and patterning layers of insulative and conductive materials on all of the exposed faces in the fixture; and (e) severing the layers between the faces in the space provided by the spacers. With this process, beading effects in materials that are spun onto the assemblies are eliminated; handling damage to the assemblies is eliminated; and the time and expense of processing one assembly separately is cut by several hundred percent.
申请公布号 US4999311(A) 申请公布日期 1991.03.12
申请号 US19890395237 申请日期 1989.08.16
申请人 UNISYS CORPORATION 发明人 DZARNOSKI, JR., JOHN E.;BABCOCK, JAMES W.
分类号 H01L21/00 主分类号 H01L21/00
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